/****************************************************************************
 * @file    : NSUC16x0.h
 * @author  : novosense
 * @version : V2.0
 * @Date    : 2023/4/10
 * @brief   : register define header file
 * @note
 * Copyright (C) 2023 novosense All rights reserved.
 ****************************************************************************/
#ifndef __NSUC16x0_H
#define __NSUC16x0_H


// ------------------------------------------------------------------------//
// Includes
// -------------------------------------------------------------------------//
#include "typedef.h"
#include <stdint.h>

#define HRPWM_MODE              0
#define SYSCTRL_UNLOCK_KEY      0x87e4


#define EFLASH_BASE             ((uint32_t)0x08000000) /*!< EFLASH base address in the alias region */
#define SRAM_BASE               ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE             ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define APB_BASE                (PERIPH_BASE          )
#define AHB_BASE                (PERIPH_BASE + 0x20000)
#define EEPROMMEM_BASE          (AHB_BASE + 0x2000)
#define EEPROMREG_BASE          (AHB_BASE + 0x2300)


// AliasAddr = 0x22000000+((A-0x20000000)*8+n)*4 = 0x22000000+ (A-0x20000000)*32 + n*4
#define BITBAND(addr, bit)      (*(__IO int32_t *)(0x22000000+((addr-0x20000000)*8+bit)*4))

/** unsigned integer 8-bit */
typedef unsigned char   u8;

/** unsigned integer 16-bit */
typedef unsigned short  u16;

/** unsigned integer 32-bit */
typedef unsigned int    u32;

/** signed integer 8-bit */
typedef signed char    i8;

/** signed integer 16-bit */
typedef signed short    i16;

/** signed integer 32-bit */
typedef signed int    i32;

/** @}  end of group Data-Types */  


/*****************************************************************************/
/** @addtogroup Bit-Definitions
 *  @{ */
/*****************************************************************************/
#define BIT_31    (0x80000000UL)
#define BIT_30    (0x40000000UL)
#define BIT_29    (0x20000000UL)
#define BIT_28    (0x10000000UL)
#define BIT_27    (0x08000000UL)
#define BIT_26    (0x04000000UL)
#define BIT_25    (0x02000000UL)
#define BIT_24    (0x01000000UL)

#define BIT_23    (0x00800000UL)
#define BIT_22    (0x00400000UL)
#define BIT_21    (0x00200000UL)
#define BIT_20    (0x00100000UL)
#define BIT_19    (0x00080000UL)
#define BIT_18    (0x00040000UL)
#define BIT_17    (0x00020000UL)
#define BIT_16    (0x00010000UL)

#define BIT_15    (0x00008000UL)
#define BIT_14    (0x00004000UL)
#define BIT_13    (0x00002000UL)
#define BIT_12    (0x00001000UL)
#define BIT_11    (0x00000800UL)
#define BIT_10    (0x00000400UL)
#define BIT_9     (0x00000200UL)
#define BIT_8     (0x00000100UL)

#define BIT_7     (0x00000080UL)
#define BIT_6     (0x00000040UL)
#define BIT_5     (0x00000020UL)
#define BIT_4     (0x00000010UL)
#define BIT_3     (0x00000008UL)
#define BIT_2     (0x00000004UL)
#define BIT_1     (0x00000002UL)
#define BIT_0     (0x00000001UL)


/*
 * ==========================================================================
 * ---------- Interrupt Number Definition -----------------------------------
 * ==========================================================================
 */

typedef enum IRQn {
    /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
    NonMaskableInt_IRQn           = -14,    /*!<  2 Cortex-M3 Non Maskable Interrupt                        */
    HardFault_IRQn                = -13,    /*!<  3 Cortex-M3 Hard Fault Interrupt                          */
    MemoryManagement_IRQn         = -12,    /*!<  4 Cortex-M3 Memory Management Interrupt            */
    BusFault_IRQn                 = -11,    /*!<  5 Cortex-M3 Bus Fault Interrupt                    */
    UsageFault_IRQn               = -10,    /*!<  6 Cortex-M3 Usage Fault Interrupt                  */
    SVCall_IRQn                   = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                      */
    DebugMonitor_IRQn             = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                */
    PendSV_IRQn                   = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                      */
    SysTick_IRQn                  = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                  */

    /******  CM3DS_MPS2 Specific Interrupt Numbers *******************************************************/
    GPIO_IRQn                     = 0,   /*!< GPIO全局中断 */
    TMR0_IRQn                     = 1,   /*!< TIMER0全局中断 */
    TMR1_IRQn                     = 2,   /*!< TIMER1全局中断 */
    LINUART_IRQn                  = 3,   /*!< LINUART全局中断 */
    EPWM0_IRQn                    = 4,   /*!< EPWM0全局中断 */
    EPWM1_IRQn                    = 5,   /*!< EPWM1全局中断 */
    EPWM2_IRQn                    = 6,   /*!< EPWM2全局中断 */
    EPWM3_IRQn                    = 7,   /*!< EPWM3全局中断 */
    CAPCOM0_IRQn                  = 8,   /*!< CAPCOM0全局中断 */
    CAPCOM1_IRQn                  = 9,   /*!< CAPCOM1全局中断 */
    CAPCOM2_IRQn                  = 10,   /*!< CAPCOM2全局中断 */
    ADC_IRQn                      = 11,   /*!< ADC全局中断 */
    BEMFC_IRQn                    = 12,   /*!< BEMFC全局中断 */
    SPI_IRQn                      = 13,   /*!< SPI全局中断 */
    FLASH_ECC_IRQn                = 14,   /*!< FLASH_ECC全局中断 */
    PWMIO_IRQn                    = 15,   /*!< PWMIO全局中断 */
    LINPORT_IRQn                  = 16,   /*!< LINPORT全局中断 */
    RFI_IRQn                      = 17,   /*!< RFI全局中断 */
    HSBVDD_IRQn                   = 18,   /*!< HCBVDD全局中断 */
    PMU_IRQn                      = 19,   /*!< PMU全局中断 */
    CHP_IRQn                      = 20,   /*!< CHARGEPUMP中断 */
} IRQn_Type;


/* ==========================================================================
 * ----------- Processor and Core Peripheral Section ------------------------
 * ==========================================================================
 */

/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __CM3_REV                 0x0201    /*!< Core Revision r2p1                             */
#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels        */
#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used   */
#define __MPU_PRESENT             1         /*!< MPU present or not                             */

#include "core_cm3.h"
#pragma anon_unions
/**
  * @brief Flash_Controller (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t FCR;                 /*!< Address Offset: 0x000  FLASH Control Register  */
         struct {
            __IO uint32_t WLA                :  1;
            __IO uint32_t WNV                :  1;
            __IO uint32_t ERA                :  1;
            __IO uint32_t SBIE               :  1;
            __IO uint32_t DBIE               :  1;
            __IO uint32_t                    :  1;
            __IO uint32_t WKP                :  1;
            __IO uint32_t STD                :  1;
            __IO uint32_t TEST               :  1;
            __IO uint32_t                    : 20;
            __IO uint32_t ULKCFG             :  1;
            __IO uint32_t ULKREG             :  1;
            __IO uint32_t LOCK               :  1;
        } FCR_b;
    };
    union {
        __IO uint32_t FSR;                 /*!< Address Offset: 0x004  FLASH Status Register  */
         struct {
            __IO uint32_t SBC                :  1;
            __IO uint32_t DBC                :  1;
            __IO uint32_t BUSY               :  1;
            __IO uint32_t                    : 29;
        } FSR_b;
    };
    union {
        __IO uint32_t OKR;                 /*!< Address Offset: 0x008  FLASH Option Key Register  */
         struct {
            __IO uint32_t KEY                : 32;
        } OKR_b;
    };
    __IO uint32_t reserved0;
    union {
        __IO uint32_t ETR;                 /*!< Address Offset: 0x010  FLASH Timing Register  */
         struct {
            __IO uint32_t UNIT               :  6;
            __IO uint32_t NVS                :  2;
            __IO uint32_t RC                 :  2;
            __IO uint32_t                    : 22;
        } ETR_b;
    };
} FLASH_CONTROLLER_TypeDef;
/**
  * @brief SYSCTRL (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t SCCR;                 /*!< Address Offset: 0x000  SYSCTRL System Clock Control Register   */
         struct {
            __IO uint32_t SYSCDIV            :  3;
            __IO uint32_t SCKSRC             :  1;
            __IO uint32_t AHBAGE             :  1;
            __IO uint32_t                    : 11;
            __IO uint32_t APBCEN             :  1;
            __IO uint32_t AHBCEN             :  1;
            __IO uint32_t APBRST             :  1;
            __IO uint32_t AHBRST             :  1;
            __IO uint32_t FHRRST             :  1;
            __IO uint32_t                    : 11;
        } SCCR_b;
    };
    union {
        __IO uint32_t APBCGR;                 /*!< Address Offset: 0x004  SYSCTRL APB Clock Gate Register   */
         struct {
            __IO uint32_t SPICEN             :  1;
            __IO uint32_t LINUCEN            :  1;
            __IO uint32_t LINPCEN            :  1;
            __IO uint32_t PIOCEN             :  1;
            __IO uint32_t TMR0CEN            :  1;
            __IO uint32_t TMR1CEN            :  1;
            __IO uint32_t CAPCMPCEN          :  1;
            __IO uint32_t                    : 25;
        } APBCGR_b;
    };
    union {
        __IO uint32_t AHBCGR;                 /*!< Address Offset: 0x008  SYSCTRL AHB Clock Gate Register   */
         struct {
            __IO uint32_t EPRCEN             :  1;
            __IO uint32_t GPIOCEN            :  1;
            __IO uint32_t ADCCEN             :  1;
            __IO uint32_t DACCEN             :  1;
            __IO uint32_t PWMCEN             :  1;
            __IO uint32_t                    : 27;
        } AHBCGR_b;
    };
    __IO uint32_t reserved0;
    union {
        __IO uint32_t APBSRR;                 /*!< Address Offset: 0x010  SYSCTRL APB SoftReset Register   */
         struct {
            __IO uint32_t SPIREN             :  1;
            __IO uint32_t LINUREN            :  1;
            __IO uint32_t LINPREN            :  1;
            __IO uint32_t PIOREN             :  1;
            __IO uint32_t TMR0REN            :  1;
            __IO uint32_t TMR1REN            :  1;
            __IO uint32_t CAPCMPREN          :  1;
            __IO uint32_t                    : 25;
        } APBSRR_b;
    };
    union {
        __IO uint32_t AHBSRR;                 /*!< Address Offset: 0x014  SYSCTRL APB SoftReset Register   */
         struct {
            __IO uint32_t FLSREN             :  1;
            __IO uint32_t GPIOREN            :  1;
            __IO uint32_t ADCREN             :  1;
            __IO uint32_t DACREN             :  1;
            __IO uint32_t PWMREN             :  1;
            __IO uint32_t                    : 27;
        } AHBSRR_b;
    };
    __IO uint32_t reserved1;
    __IO uint32_t reserved2;
    union {
        __IO uint32_t SYSWKR;                 /*!< Address Offset: 0x020  SYSCTRL System Wakeup Register   */
         struct {
            __IO uint32_t BVDDUVE            :  1;
            __IO uint32_t BVDDOVE            :  1;
            __IO uint32_t LINWKE             :  1;
            __IO uint32_t WTWKE              :  1;
            __IO uint32_t LINWDBC            :  2;
            __IO uint32_t LINDEN             :  1;
            __IO uint32_t                    : 25;
        } SYSWKR_b;
    };
    union {
        __IO uint32_t SYSSTR;                 /*!< Address Offset: 0x024  SYSCTRL System Status Register   */
         struct {
            __IO uint32_t BVDDUV             :  1;
            __IO uint32_t BVDDOV             :  1;
            __IO uint32_t LINWK              :  1;
            __IO uint32_t WTWK               :  1;
            __IO uint32_t FHRST              :  1;
            __IO uint32_t PMUST              :  1;
            __IO uint32_t SQRST              :  1;
            __IO uint32_t DWRST              :  1;
            __IO uint32_t WWRST              :  1;
            __IO uint32_t                    : 23;
        } SYSSTR_b;
    };
    union {
        __IO uint32_t PWRCR;                 /*!< Address Offset: 0x028  SYSCTRL Power Control Register   */
         struct {
            __IO uint32_t BUF                :  4;
            __IO uint32_t BOF                :  4;
            __IO uint32_t TSF                :  4;
            __IO uint32_t UVVTH              :  2;
            __IO uint32_t                    :  2;
            __IO uint32_t BUBEN              :  1;
            __IO uint32_t BOBEN              :  1;
            __IO uint32_t TSBEN              :  1;
            __IO uint32_t                    :  1;
            __IO uint32_t BUIEN              :  1;
            __IO uint32_t BOIEN              :  1;
            __IO uint32_t TSIEN              :  1;
            __IO uint32_t                    :  1;
            __IO uint32_t BUREN              :  1;
            __IO uint32_t BOREN              :  1;
            __IO uint32_t TSREN              :  1;
            __IO uint32_t                    :  1;
            __IO uint32_t BUVST              :  1;
            __IO uint32_t BOVST              :  1;
            __IO uint32_t TSDST              :  1;
            __IO uint32_t RFIST              :  1;
        } PWRCR_b;
    };
    union {
        __IO uint32_t APMUSTR;                 /*!< Address Offset: 0x02C  SYSCTRL APMU Status Register  */
         struct {
            __IO uint32_t STAR               :  6;
            __IO uint32_t                    : 26;
        } APMUSTR_b;
    };
    union {
        __IO uint32_t LPCR;                 /*!< Address Offset: 0x030  SYSCTRL LowpowerContorl Register  */
         struct {
            __IO uint32_t IDLE               :  1;
            __IO uint32_t SLEEP              :  1;
            __IO uint32_t SHAE               :  1;
            __IO uint32_t                    : 29;
        } LPCR_b;
    };
    union {
        __IO uint32_t HCR;                 /*!< Address Offset: 0x034  SYSCTRL HSBVDD Contorl Register   */
         struct {
            __IO uint32_t HSEN               :  1;
            __IO uint32_t DO                 :  1;
            __IO uint32_t ABE                :  1;
            __IO uint32_t HIE                :  1;
            __IO uint32_t FT                 :  2;
            __IO uint32_t BFE                :  1;
            __IO uint32_t IS                 :  1;
            __IO uint32_t CE                 :  1;
            __IO uint32_t CAE                :  1;
            __IO uint32_t CF                 :  2;
            __IO uint32_t CFE                :  1;
            __IO uint32_t CIE                :  1;
            __IO uint32_t CS                 :  1;
            __IO uint32_t                    : 17;
        } HCR_b;
    };
    union {
        __IO uint32_t ANACR;                 /*!< Address Offset: 0x038  SYSCTRL Analog Config Register  */
         struct {
            __IO uint32_t MCEN               :  1;
            __IO uint32_t MCMD               :  1;
            __IO uint32_t FREQ               :  1;
            __IO uint32_t EMREN              :  1;
            __IO uint32_t ISNGC              :  2;
            __IO uint32_t VBGSEL             :  1;
            __IO uint32_t BURNIN             :  1;
            __IO uint32_t REFEN              :  1;
            __IO uint32_t                    : 23;
        } ANACR_b;
    };
    union {
        __IO uint32_t SYSDBGR;                 /*!< Address Offset: 0x03C  SYSCTRL System Debug Register   */
         struct {
            __IO uint32_t DWDGDE             :  1;
            __IO uint32_t WWDGDE             :  1;
            __IO uint32_t TMR0DE             :  1;
            __IO uint32_t TMR1DE             :  1;
            __IO uint32_t CAPDE              :  1;
            __IO uint32_t ADCDE              :  1;
            __IO uint32_t PWMDE              :  1;
            __IO uint32_t PIODE              :  1;
            __IO uint32_t SPIDE              :  1;
            __IO uint32_t LINDEN             :  1;
            __IO uint32_t                    : 22;
        } SYSDBGR_b;
    };
    union {
        __IO uint32_t LKKEYR;                 /*!< Address Offset: 0x040  SYSCTRL LockKey Register  */
         struct {
            __IO uint32_t LOCKKEY            : 16;
            __IO uint32_t KEYST0             :  1;
            __IO uint32_t KEYST1             :  1;
            __IO uint32_t                    : 14;
        } LKKEYR_b;
    };
    union {
        __IO uint32_t SYSDTBR;                 /*!< Address Offset: 0x044  System Design Test Register  */
         struct {
            __IO uint32_t ATBEN              :  2;
            __IO uint32_t LCEN               :  1;
            __IO uint32_t LINTM              :  2;
            __IO uint32_t CH1IMX             :  1;
            __IO uint32_t CH2IMX             :  1;
            __IO uint32_t CH3IMX             :  1;
            __IO uint32_t CH4IMX             :  1;
            __IO uint32_t CH1OCP             :  2;
            __IO uint32_t CH2OCP             :  2;
            __IO uint32_t CH3OCP             :  2;
            __IO uint32_t CH4OCP             :  2;
            __IO uint32_t OVSTL              :  1;
            __IO uint32_t OVSTH              :  1;
            __IO uint32_t                    :  1;
            __IO uint32_t TCLKEN             :  1;
            __IO uint32_t DBGEN              :  1;
            __IO uint32_t DBGSRC             :  5;
            __IO uint32_t TMUX               :  5;
        } SYSDTBR_b;
    };
    __IO uint32_t reserved3;
    __IO uint32_t reserved4;
    __IO uint32_t reserved5;
    __IO uint32_t reserved6;
    __IO uint32_t reserved7;
    __IO uint32_t reserved8;
    union {
        __IO uint32_t SYSCFR;                 /*!< Address Offset: 0x060  SYSCTRL Config Register  */
         struct {
            __IO uint32_t SWEN               :  4;
            __IO uint32_t DWDGEN             :  4;
            __IO uint32_t WWDGEN             :  4;
            __IO uint32_t                    : 20;
        } SYSCFR_b;
    };
    union {
        __IO uint32_t CHIPID;                 /*!< Address Offset: 0x064  SYSCTRL CHIPID Register  */
         struct {
            __IO uint32_t CID                : 32;
        } CHIPID_b;
    };
    __IO uint32_t reserved9;
    __IO uint32_t reserved10;
    union {
        __IO uint32_t UID0R;                 /*!< Address Offset: 0x070  SYSCTRL Chip ID Register 0   */
         struct {
            __IO uint32_t UID0               : 32;
        } UID0R_b;
    };
    union {
        __IO uint32_t UID1R;                 /*!< Address Offset: 0x074  SYSCTRL Chip ID Register 1   */
         struct {
            __IO uint32_t UID1               : 32;
        } UID1R_b;
    };
    union {
        __IO uint32_t UID2R;                 /*!< Address Offset: 0x078  SYSCTRL Chip ID Register 2   */
         struct {
            __IO uint32_t UID2               : 32;
        } UID2R_b;
    };
    union {
        __IO uint32_t UID3R;                 /*!< Address Offset: 0x07C  SYSCTRL Chip ID Register 3  */
         struct {
            __IO uint32_t UID3               : 32;
        } UID3R_b;
    };
} SYSCTRL_TypeDef;
/**
  * @brief GPIO (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t BSR;                 /*!< Address Offset: 0x000  GPIO BIT Set/Reset Register   */
         struct {
            __IO uint32_t BS0                :  1;
            __IO uint32_t BS1                :  1;
            __IO uint32_t BS2                :  1;
            __IO uint32_t BS3                :  1;
            __IO uint32_t BS4                :  1;
            __IO uint32_t BS5                :  1;
            __IO uint32_t BS6                :  1;
            __IO uint32_t BS7                :  1;
            __IO uint32_t BS8                :  1;
            __IO uint32_t BS9                :  1;
            __IO uint32_t BS10               :  1;
            __IO uint32_t                    :  5;
            __IO uint32_t BR0                :  1;
            __IO uint32_t BR1                :  1;
            __IO uint32_t BR2                :  1;
            __IO uint32_t BR3                :  1;
            __IO uint32_t BR4                :  1;
            __IO uint32_t BR5                :  1;
            __IO uint32_t BR6                :  1;
            __IO uint32_t BR7                :  1;
            __IO uint32_t BR8                :  1;
            __IO uint32_t BR9                :  1;
            __IO uint32_t BR10               :  1;
            __IO uint32_t                    :  5;
        } BSR_b;
    };
    union {
        __IO uint32_t PDI;                 /*!< Address Offset: 0x004  GPIO Input Register  */
         struct {
            __IO uint32_t DI0                :  1;
            __IO uint32_t DI1                :  1;
            __IO uint32_t DI2                :  1;
            __IO uint32_t DI3                :  1;
            __IO uint32_t DI4                :  1;
            __IO uint32_t DI5                :  1;
            __IO uint32_t DI6                :  1;
            __IO uint32_t DI7                :  1;
            __IO uint32_t DI8                :  1;
            __IO uint32_t DI9                :  1;
            __IO uint32_t DI10               :  1;
            __IO uint32_t                    : 21;
        } PDI_b;
    };
    union {
        __IO uint32_t PDO;                 /*!< Address Offset: 0x008  GPIO Output Register  */
         struct {
            __IO uint32_t DO0                :  1;
            __IO uint32_t DO1                :  1;
            __IO uint32_t DO2                :  1;
            __IO uint32_t DO3                :  1;
            __IO uint32_t DO4                :  1;
            __IO uint32_t DO5                :  1;
            __IO uint32_t DO6                :  1;
            __IO uint32_t DO7                :  1;
            __IO uint32_t DO8                :  1;
            __IO uint32_t DO9                :  1;
            __IO uint32_t DO10               :  1;
            __IO uint32_t                    : 21;
        } PDO_b;
    };
    __IO uint32_t reserved0;
    union {
        __IO uint32_t IEN;                 /*!< Address Offset: 0x010  GPIO Interruput Enable Register  */
         struct {
            __IO uint32_t IEN0               :  1;
            __IO uint32_t IEN1               :  1;
            __IO uint32_t IEN2               :  1;
            __IO uint32_t IEN3               :  1;
            __IO uint32_t IEN4               :  1;
            __IO uint32_t IEN5               :  1;
            __IO uint32_t IEN6               :  1;
            __IO uint32_t IEN7               :  1;
            __IO uint32_t IEN8               :  1;
            __IO uint32_t IEN9               :  1;
            __IO uint32_t IEN10              :  1;
            __IO uint32_t                    : 21;
        } IEN_b;
    };
    union {
        __IO uint32_t ICR;                 /*!< Address Offset: 0x014  GPIO Interrupt  Mode Register   */
         struct {
            __IO uint32_t UD0                :  2;
            __IO uint32_t UD1                :  2;
            __IO uint32_t UD2                :  2;
            __IO uint32_t UD3                :  2;
            __IO uint32_t UD4                :  2;
            __IO uint32_t UD5                :  2;
            __IO uint32_t UD6                :  2;
            __IO uint32_t UD7                :  2;
            __IO uint32_t UD8                :  2;
            __IO uint32_t UD9                :  2;
            __IO uint32_t UD10               :  2;
            __IO uint32_t                    : 10;
        } ICR_b;
    };
    union {
        __IO uint32_t IPND;                 /*!< Address Offset: 0x018  GPIO Pending Register   */
         struct {
            __IO uint32_t PD0                :  1;
            __IO uint32_t PD1                :  1;
            __IO uint32_t PD2                :  1;
            __IO uint32_t PD3                :  1;
            __IO uint32_t PD4                :  1;
            __IO uint32_t PD5                :  1;
            __IO uint32_t PD6                :  1;
            __IO uint32_t PD7                :  1;
            __IO uint32_t PD8                :  1;
            __IO uint32_t PD9                :  1;
            __IO uint32_t PD10               :  1;
            __IO uint32_t                    : 21;
        } IPND_b;
    };
    union {
        __IO uint32_t EIPND;                 /*!< Address Offset: 0x01C  GPIO Enable Pending Register   */
         struct {
            __IO uint32_t EPD0               :  1;
            __IO uint32_t EPD1               :  1;
            __IO uint32_t EPD2               :  1;
            __IO uint32_t EPD3               :  1;
            __IO uint32_t EPD4               :  1;
            __IO uint32_t EPD5               :  1;
            __IO uint32_t EPD6               :  1;
            __IO uint32_t EPD7               :  1;
            __IO uint32_t EPD8               :  1;
            __IO uint32_t EPD9               :  1;
            __IO uint32_t EPD10              :  1;
            __IO uint32_t                    : 21;
        } EIPND_b;
    };
    union {
        __IO uint32_t MXR;                 /*!< Address Offset: 0x020  GPIO Pinmux Register 0   */
         struct {
            __IO uint32_t PM0                :  4;
            __IO uint32_t PM1                :  4;
            __IO uint32_t PM2                :  4;
            __IO uint32_t PM3                :  4;
            __IO uint32_t PM4                :  4;
            __IO uint32_t PM5                :  4;
            __IO uint32_t PM6                :  4;
            __IO uint32_t PM7                :  4;
        } MXR_b;
    };
    union {
        __IO uint32_t MYR;                 /*!< Address Offset: 0x024  GPIO Pinmux Register 1   */
         struct {
            __IO uint32_t PM8                :  4;
            __IO uint32_t PM9                :  4;
            __IO uint32_t PM10               :  4;
            __IO uint32_t                    : 20;
        } MYR_b;
    };
    union {
        __IO uint32_t DER;                 /*!< Address Offset: 0x028  GPIO Debounce Enable Register  */
         struct {
            __IO uint32_t DE0                :  1;
            __IO uint32_t DE1                :  1;
            __IO uint32_t DE2                :  1;
            __IO uint32_t DE3                :  1;
            __IO uint32_t DE4                :  1;
            __IO uint32_t DE5                :  1;
            __IO uint32_t DE6                :  1;
            __IO uint32_t DE7                :  1;
            __IO uint32_t DE8                :  1;
            __IO uint32_t DE9                :  1;
            __IO uint32_t DE10               :  1;
            __IO uint32_t                    : 21;
        } DER_b;
    };
    union {
        __IO uint32_t DTR;                 /*!< Address Offset: 0x02C  GPIO Debounce Time Register  */
         struct {
            __IO uint32_t DT                 :  3;
            __IO uint32_t                    : 29;
        } DTR_b;
    };
    union {
        __IO uint32_t PUR;                 /*!< Address Offset: 0x030  GPIO Pull-up enable register   */
         struct {
            __IO uint32_t PU0                :  1;
            __IO uint32_t PU1                :  1;
            __IO uint32_t PU2                :  1;
            __IO uint32_t PU3                :  1;
            __IO uint32_t PU4                :  1;
            __IO uint32_t PU5                :  1;
            __IO uint32_t PU6                :  1;
            __IO uint32_t PU7                :  1;
            __IO uint32_t PU8                :  1;
            __IO uint32_t PU9                :  1;
            __IO uint32_t PU10               :  1;
            __IO uint32_t                    : 21;
        } PUR_b;
    };
    union {
        __IO uint32_t PDR;                 /*!< Address Offset: 0x034  GPIO Pull-down enable register   */
         struct {
            __IO uint32_t PD0                :  1;
            __IO uint32_t PD1                :  1;
            __IO uint32_t PD2                :  1;
            __IO uint32_t PD3                :  1;
            __IO uint32_t PD4                :  1;
            __IO uint32_t PD5                :  1;
            __IO uint32_t PD6                :  1;
            __IO uint32_t PD7                :  1;
            __IO uint32_t PD8                :  1;
            __IO uint32_t PD9                :  1;
            __IO uint32_t PD10               :  1;
            __IO uint32_t                    : 21;
        } PDR_b;
    };
    union {
        __IO uint32_t ODR;                 /*!< Address Offset: 0x038  GPIO Open Drain Register  */
         struct {
            __IO uint32_t OD0                :  1;
            __IO uint32_t OD1                :  1;
            __IO uint32_t OD2                :  1;
            __IO uint32_t OD3                :  1;
            __IO uint32_t OD4                :  1;
            __IO uint32_t OD5                :  1;
            __IO uint32_t OD6                :  1;
            __IO uint32_t OD7                :  1;
            __IO uint32_t OD8                :  1;
            __IO uint32_t OD9                :  1;
            __IO uint32_t OD10               :  1;
            __IO uint32_t                    : 21;
        } ODR_b;
    };
} GPIO_TypeDef;
/**
  * @brief EEPROM_CTRL (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t ECR;                 /*!< Address Offset: 0x000  EEPROM Control Register  */
         struct {
            __IO uint32_t WLA                :  1;
            __IO uint32_t ERA                :  1;
            __IO uint32_t SBIE               :  1;
            __IO uint32_t DBIE               :  1;
            __IO uint32_t                    : 25;
            __IO uint32_t TCFGX              :  1;
            __IO uint32_t TCFGY              :  1;
            __IO uint32_t LOCK               :  1;
        } ECR_b;
    };
    union {
        __IO uint32_t FSR;                 /*!< Address Offset: 0x004  EEPROM Status Register  */
         struct {
            __IO uint32_t SBC                :  1;
            __IO uint32_t DBC                :  1;
            __IO uint32_t BUSY               :  1;
            __IO uint32_t                    : 29;
        } FSR_b;
    };
    union {
        __IO uint32_t OKR;                 /*!< Address Offset: 0x008  EEPROM Option Key Register  */
         struct {
            __IO uint32_t KEY                : 32;
        } OKR_b;
    };
    __IO uint32_t reserved0;
    union {
        __IO uint32_t KEY;                 /*!< Address Offset: 0x010  EEPROM Timing Register  */
         struct {
            __IO uint32_t WRT                :  7;
            __IO uint32_t                    :  1;
            __IO uint32_t WHT                :  4;
            __IO uint32_t                    : 20;
        } KEY_b;
    };
} EEPROM_CTRL_TypeDef;
/**
  * @brief ADC (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t CR;                 /*!< Address Offset: 0x000  ADC Control Register  */
         struct {
            __IO uint32_t EN                 :  1;
            __IO uint32_t TTEN               :  1;
            __IO uint32_t                    :  1;
            __IO uint32_t SWT                :  1;
            __IO uint32_t TSRC               :  3;
            __IO uint32_t BUSY               :  1;
            __IO uint32_t CKSEL              :  4;
            __IO uint32_t                    :  4;
            __IO uint32_t TESTEN             :  1;
            __IO uint32_t TESTSEL            :  1;
            __IO uint32_t                    : 14;
        } CR_b;
    };
    union {
        __IO uint32_t TTP;                 /*!< Address Offset: 0x004  ADC Trigger Timer Period Register  */
         struct {
            __IO uint32_t TPER               : 12;
            __IO uint32_t                    : 20;
        } TTP_b;
    };
    union {
        __IO uint32_t SCR;                 /*!< Address Offset: 0x008  ADC Sample Configuration Register  */
         struct {
            __IO uint32_t SAMP               :  6;
            __IO uint32_t                    :  2;
            __IO uint32_t CONV               :  6;
            __IO uint32_t                    :  2;
            __IO uint32_t STABLE             :  6;
            __IO uint32_t                    :  2;
            __IO uint32_t ONDLY              :  6;
            __IO uint32_t                    :  2;
        } SCR_b;
    };
    union {
        __IO uint32_t TCR;                 /*!< Address Offset: 0x00C  ADC Trim Configuration Register  */
         struct {
            __IO uint32_t REFSEL             :  2;
            __IO uint32_t                    :  2;
            __IO uint32_t PGACHOP            :  1;
            __IO uint32_t                    :  3;
            __IO uint32_t SIGEN              :  1;
            __IO uint32_t                    :  3;
            __IO uint32_t DATFMT             :  1;
            __IO uint32_t DATINV             :  1;
            __IO uint32_t OCNT               :  2;
            __IO uint32_t TRIMEN             :  1;
            __IO uint32_t                    : 15;
        } TCR_b;
    };
    union {
        __IO uint32_t QCR1;                 /*!< Address Offset: 0x010  ADC Queue Control Register 1  */
         struct {
            __IO uint32_t Q1SEL              :  4;
            __IO uint32_t Q1G                :  3;
            __IO uint32_t Q1EN               :  1;
            __IO uint32_t Q2SEL              :  4;
            __IO uint32_t Q2G                :  3;
            __IO uint32_t Q2EN               :  1;
            __IO uint32_t Q3SEL              :  4;
            __IO uint32_t Q3G                :  3;
            __IO uint32_t Q3EN               :  1;
            __IO uint32_t Q4SEL              :  4;
            __IO uint32_t Q4G                :  3;
            __IO uint32_t Q4EN               :  1;
        } QCR1_b;
    };
    union {
        __IO uint32_t QCR2;                 /*!< Address Offset: 0x014  ADC Queue Control Register 2   */
         struct {
            __IO uint32_t Q5SEL              :  4;
            __IO uint32_t Q5G                :  3;
            __IO uint32_t Q5EN               :  1;
            __IO uint32_t Q6SEL              :  4;
            __IO uint32_t Q6G                :  3;
            __IO uint32_t Q6EN               :  1;
            __IO uint32_t Q7SEL              :  4;
            __IO uint32_t Q7G                :  3;
            __IO uint32_t Q7EN               :  1;
            __IO uint32_t Q8SEL              :  4;
            __IO uint32_t Q8G                :  3;
            __IO uint32_t Q8EN               :  1;
        } QCR2_b;
    };
    union {
        __IO uint32_t OTR;                 /*!< Address Offset: 0x018  ADC Offset Trim Register  */
         struct {
            __IO uint32_t OFFTRIM_S          : 12;
            __IO uint32_t                    :  4;
            __IO uint32_t OFFTRIM_D          : 12;
            __IO uint32_t                    :  4;
        } OTR_b;
    };
    union {
        __IO uint32_t GTR;                 /*!< Address Offset: 0x01C  ADC Gain Trim Register  */
         struct {
            __IO uint32_t GAINTRIM_S         : 14;
            __IO uint32_t                    :  2;
            __IO uint32_t GAINTRIM_D         : 14;
            __IO uint32_t                    :  2;
        } GTR_b;
    };
    union {
        __IO uint32_t DR1;                 /*!< Address Offset: 0x020  ADC Data Register 1  */
         struct {
            __IO uint32_t DATA               : 16;
            __IO uint32_t                    : 16;
        } DR1_b;
    };
    union {
        __IO uint32_t DR2;                 /*!< Address Offset: 0x024  ADC Data Register 2   */
         struct {
            __IO uint32_t DATA               : 16;
            __IO uint32_t                    : 16;
        } DR2_b;
    };
    union {
        __IO uint32_t DR3;                 /*!< Address Offset: 0x028  ADC Data Register 3   */
         struct {
            __IO uint32_t DATA               : 16;
            __IO uint32_t                    : 16;
        } DR3_b;
    };
    union {
        __IO uint32_t DR4;                 /*!< Address Offset: 0x02C  ADC Data Register 4   */
         struct {
            __IO uint32_t DATA               : 16;
            __IO uint32_t                    : 16;
        } DR4_b;
    };
    union {
        __IO uint32_t DR5;                 /*!< Address Offset: 0x030  ADC Data Register 5   */
         struct {
            __IO uint32_t DATA               : 16;
            __IO uint32_t                    : 16;
        } DR5_b;
    };
    union {
        __IO uint32_t DR6;                 /*!< Address Offset: 0x034  ADC Data Register 6   */
         struct {
            __IO uint32_t DATA               : 16;
            __IO uint32_t                    : 16;
        } DR6_b;
    };
    union {
        __IO uint32_t DR7;                 /*!< Address Offset: 0x038  ADC Data Register 7   */
         struct {
            __IO uint32_t DATA               : 16;
            __IO uint32_t                    : 16;
        } DR7_b;
    };
    union {
        __IO uint32_t DR8;                 /*!< Address Offset: 0x03C  ADC Data Register 8   */
         struct {
            __IO uint32_t DATA               : 16;
            __IO uint32_t                    : 16;
        } DR8_b;
    };
    union {
        __IO uint32_t IEN;                 /*!< Address Offset: 0x040  ADC Interrupt Enable Register  */
         struct {
            __IO uint32_t EOC                :  1;
            __IO uint32_t TCOLL              :  1;
            __IO uint32_t                    : 30;
        } IEN_b;
    };
    union {
        __IO uint32_t IPND;                 /*!< Address Offset: 0x044  ADC Interrupt Pending Register  */
         struct {
            __IO uint32_t EOC                :  1;
            __IO uint32_t TCOLL              :  1;
            __IO uint32_t                    : 30;
        } IPND_b;
    };
    union {
        __IO uint32_t EIPND;                 /*!< Address Offset: 0x048  ADC Enabled Interrupt Pending Register  */
         struct {
            __IO uint32_t EOC                :  1;
            __IO uint32_t TCOLL              :  1;
            __IO uint32_t                    : 30;
        } EIPND_b;
    };
    __IO uint32_t reserved0;
    __IO uint32_t reserved1;
    __IO uint32_t reserved2;
    union {
        __IO uint32_t PTR;                 /*!< Address Offset: 0x058  ADC PGA Trim Register  */
         struct {
            __IO uint32_t PGA                :  8;
            __IO uint32_t                    : 24;
        } PTR_b;
    };
    union {
        __IO uint32_t TPSR;                 /*!< Address Offset: 0x05C  ADC Temperature Sensor Trim Register  */
         struct {
            __IO uint32_t TST                : 12;
            __IO uint32_t TSA                : 12;
            __IO uint32_t                    :  8;
        } TPSR_b;
    };
    union {
        __IO uint32_t WCR0;                 /*!< Address Offset: 0x060  ADC Weight Coeff Register 0   */
         struct {
            __IO uint32_t WCOEF              : 14;
            __IO uint32_t                    : 18;
        } WCR0_b;
    };
    union {
        __IO uint32_t WCR1;                 /*!< Address Offset: 0x064  ADC Weight Coeff Register 1   */
         struct {
            __IO uint32_t WCOEF              : 14;
            __IO uint32_t                    : 18;
        } WCR1_b;
    };
    union {
        __IO uint32_t WCR2;                 /*!< Address Offset: 0x068  ADC Weight Coeff Register 2  */
         struct {
            __IO uint32_t WCOEF              : 15;
            __IO uint32_t                    : 17;
        } WCR2_b;
    };
    union {
        __IO uint32_t WCR3;                 /*!< Address Offset: 0x06C  ADC Weight Coeff Register 3  */
         struct {
            __IO uint32_t WCOEF              : 15;
            __IO uint32_t                    : 17;
        } WCR3_b;
    };
    union {
        __IO uint32_t WCR4;                 /*!< Address Offset: 0x070  ADC Weight Coeff Register 4   */
         struct {
            __IO uint32_t WCOEF              : 16;
            __IO uint32_t                    : 16;
        } WCR4_b;
    };
    union {
        __IO uint32_t WCR5;                 /*!< Address Offset: 0x074  ADC Weight Coeff Register 5   */
         struct {
            __IO uint32_t WCOEF              : 17;
            __IO uint32_t                    : 15;
        } WCR5_b;
    };
    union {
        __IO uint32_t WCR6;                 /*!< Address Offset: 0x078  ADC Weight Coeff Register 6   */
         struct {
            __IO uint32_t WCOEF              : 18;
            __IO uint32_t                    : 14;
        } WCR6_b;
    };
    union {
        __IO uint32_t WCR7;                 /*!< Address Offset: 0x07C  ADC Weight Coeff Register 7  */
         struct {
            __IO uint32_t WCOEF              : 19;
            __IO uint32_t                    : 13;
        } WCR7_b;
    };
    union {
        __IO uint32_t WCR8;                 /*!< Address Offset: 0x080  ADC Weight Coeff Register 8  */
         struct {
            __IO uint32_t WCOEF              : 19;
            __IO uint32_t                    : 13;
        } WCR8_b;
    };
    union {
        __IO uint32_t WCR9;                 /*!< Address Offset: 0x084  ADC Weight Coeff Register 9   */
         struct {
            __IO uint32_t WCOEF              : 20;
            __IO uint32_t                    : 12;
        } WCR9_b;
    };
    union {
        __IO uint32_t WCR10;                 /*!< Address Offset: 0x088  ADC Weight Coeff Register 10   */
         struct {
            __IO uint32_t WCOEF              : 21;
            __IO uint32_t                    : 11;
        } WCR10_b;
    };
    union {
        __IO uint32_t WCR11;                 /*!< Address Offset: 0x08C  ADC Weight Coeff Register 11   */
         struct {
            __IO uint32_t WCOEF              : 22;
            __IO uint32_t                    : 10;
        } WCR11_b;
    };
    union {
        __IO uint32_t WCR12;                 /*!< Address Offset: 0x090  ADC Weight Coeff Register 12   */
         struct {
            __IO uint32_t WCOEF              : 23;
            __IO uint32_t                    :  9;
        } WCR12_b;
    };
    union {
        __IO uint32_t WCR13;                 /*!< Address Offset: 0x094  ADC Weight Coeff Register 13   */
         struct {
            __IO uint32_t WCOEF              : 24;
            __IO uint32_t                    :  8;
        } WCR13_b;
    };
    union {
        __IO uint32_t WCR14;                 /*!< Address Offset: 0x098  ADC Weight Coeff Register 14   */
         struct {
            __IO uint32_t WCOEF              : 25;
            __IO uint32_t                    :  7;
        } WCR14_b;
    };
    union {
        __IO uint32_t WCR15;                 /*!< Address Offset: 0x09C  ADC Weight Coeff Register 15  */
         struct {
            __IO uint32_t WCOEF              : 25;
            __IO uint32_t                    :  7;
        } WCR15_b;
    };
} ADC_TypeDef;
/**
  * @brief BEMFC (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t CR0;                 /*!< Address Offset: 0x000  BEMFC Control Register 0  */
         struct {
            __IO uint32_t EN0                :  1;
            __IO uint32_t EN1                :  1;
            __IO uint32_t EN2                :  1;
            __IO uint32_t                    :  1;
            __IO uint32_t BLKT0              :  4;
            __IO uint32_t BLKT1              :  4;
            __IO uint32_t BLKT2              :  4;
            __IO uint32_t INV0               :  1;
            __IO uint32_t INV1               :  1;
            __IO uint32_t INV2               :  1;
            __IO uint32_t                    :  1;
            __IO uint32_t DGL0               :  2;
            __IO uint32_t                    :  2;
            __IO uint32_t DGL1               :  2;
            __IO uint32_t                    :  2;
            __IO uint32_t DGL2               :  2;
            __IO uint32_t                    :  2;
        } CR0_b;
    };
    union {
        __IO uint32_t CR1;                 /*!< Address Offset: 0x004  BEMFC Control Register 1  */
         struct {
            __IO uint32_t ITS0               :  2;
            __IO uint32_t DTP0               :  2;
            __IO uint32_t DTS0               :  5;
            __IO uint32_t                    :  1;
            __IO uint32_t ITS1               :  2;
            __IO uint32_t DTP1               :  2;
            __IO uint32_t DTS1               :  5;
            __IO uint32_t                    :  1;
            __IO uint32_t ITS2               :  2;
            __IO uint32_t DTP2               :  2;
            __IO uint32_t DTS2               :  5;
            __IO uint32_t                    :  3;
        } CR1_b;
    };
    union {
        __IO uint32_t CR2;                 /*!< Address Offset: 0x008  BEMFC Control Register 2  */
         struct {
            __IO uint32_t BIS0               :  1;
            __IO uint32_t BIS1               :  1;
            __IO uint32_t BIS2               :  1;
            __IO uint32_t BRM                :  1;
            __IO uint32_t BCRM               :  2;
            __IO uint32_t                    :  2;
            __IO uint32_t HYST0              :  2;
            __IO uint32_t HYST1              :  2;
            __IO uint32_t HYST2              :  2;
            __IO uint32_t                    : 18;
        } CR2_b;
    };
    union {
        __IO uint32_t CR3;                 /*!< Address Offset: 0x00C  BEMFC Control Register 3  */
         struct {
            __IO uint32_t BCSS0              :  1;
            __IO uint32_t BCSS1              :  1;
            __IO uint32_t                    : 30;
        } CR3_b;
    };
    union {
        __IO uint32_t BCR;                 /*!< Address Offset: 0x010  BEMFC Buffer Control Register  */
         struct {
            __IO uint32_t BBE                :  1;
            __IO uint32_t BUEOP              :  1;
            __IO uint32_t BUTRG              :  1;
            __IO uint32_t                    : 29;
        } BCR_b;
    };
    union {
        __IO uint32_t SR;                 /*!< Address Offset: 0x014  BEMFC Status Register  */
         struct {
            __IO uint32_t CD0                :  1;
            __IO uint32_t CD1                :  1;
            __IO uint32_t CD2                :  1;
            __IO uint32_t                    : 29;
        } SR_b;
    };
    __IO uint32_t reserved0;
    __IO uint32_t reserved1;
    union {
        __IO uint32_t IEN;                 /*!< Address Offset: 0x020  BEMFC Interrupt Enable Register  */
         struct {
            __IO uint32_t PI0                :  1;
            __IO uint32_t PI1                :  1;
            __IO uint32_t PI2                :  1;
            __IO uint32_t                    : 29;
        } IEN_b;
    };
    union {
        __IO uint32_t IPND;                 /*!< Address Offset: 0x024  BEMFC Interrupt Pending Register  */
         struct {
            __IO uint32_t PI0                :  1;
            __IO uint32_t PI1                :  1;
            __IO uint32_t PI2                :  1;
            __IO uint32_t                    : 29;
        } IPND_b;
    };
    union {
        __IO uint32_t EIPND;                 /*!< Address Offset: 0x028  BEMFC Enabled Interrupt Pending Register  */
         struct {
            __IO uint32_t PI0                :  1;
            __IO uint32_t PI1                :  1;
            __IO uint32_t PI2                :  1;
            __IO uint32_t                    : 29;
        } EIPND_b;
    };
    __IO uint32_t reserved2;
    union {
        __IO uint32_t CLDAC_DR;                 /*!< Address Offset: 0x030  CLDAC Data Register  */
         struct {
            __IO uint32_t DATA0              :  8;
            __IO uint32_t BLT0               :  1;
            __IO uint32_t                    :  7;
            __IO uint32_t DATA1              :  8;
            __IO uint32_t BLT1               :  1;
            __IO uint32_t                    :  7;
        } CLDAC_DR_b;
    };
    union {
        __IO uint32_t CLDAC_CR;                 /*!< Address Offset: 0x034  CLDAC Control Register  */
         struct {
            __IO uint32_t EN                 :  1;
            __IO uint32_t REFSEL             :  2;
            __IO uint32_t                    : 29;
        } CLDAC_CR_b;
    };
    union {
        __IO uint32_t CLDAC_BCR;                 /*!< Address Offset: 0x038  CLDAC Buffer Control Register  */
         struct {
            __IO uint32_t CLBE               :  1;
            __IO uint32_t CLUEOP             :  1;
            __IO uint32_t CLUTRG             :  1;
            __IO uint32_t                    : 29;
        } CLDAC_BCR_b;
    };
    union {
        __IO uint32_t CLDAC_SR;                 /*!< Address Offset: 0x03C  CLDAC Status Register  */
         struct {
            __IO uint32_t OUT0               :  1;
            __IO uint32_t OUT1               :  1;
            __IO uint32_t                    : 30;
        } CLDAC_SR_b;
    };
} BEMFC_TypeDef;
/**
  * @brief EPWM (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t CR0;                 /*!< Address Offset: 0x000  EPWM Control Register 0  */
         struct {
            __IO uint32_t EN                 :  1;
            __IO uint32_t PAM                :  1;
            __IO uint32_t BCM                :  1;
            __IO uint32_t OCSDM              :  1;
            __IO uint32_t CCPT               :  4;
            __IO uint32_t CKSEL              :  4;
            __IO uint32_t OCFT               :  2;
            __IO uint32_t                    :  2;
            __IO uint32_t FSON               :  2;
            __IO uint32_t FSOFF              :  2;
            __IO uint32_t                    : 12;
        } CR0_b;
    };
    union {
        __IO uint32_t CR1;                 /*!< Address Offset: 0x004  EPWM Control Register 1  */
         struct {
            __IO uint32_t LSOM0              :  2;
            __IO uint32_t HSOM0              :  2;
            __IO uint32_t LSOM1              :  2;
            __IO uint32_t HSOM1              :  2;
            __IO uint32_t LSOM2              :  2;
            __IO uint32_t HSOM2              :  2;
            __IO uint32_t LSOM3              :  2;
            __IO uint32_t HSOM3              :  2;
            __IO uint32_t CLS0               :  2;
            __IO uint32_t CLS1               :  2;
            __IO uint32_t CLS2               :  2;
            __IO uint32_t CLS3               :  2;
            __IO uint32_t CLM0               :  1;
            __IO uint32_t CLM1               :  1;
            __IO uint32_t CLM2               :  1;
            __IO uint32_t CLM3               :  1;
            __IO uint32_t                    :  4;
        } CR1_b;
    };
    union {
        __IO uint32_t CR2;                 /*!< Address Offset: 0x008  EPWM Control Register 2  */
         struct {
            __IO uint32_t PRBE0              :  1;
            __IO uint32_t PRBE1              :  1;
            __IO uint32_t PRBE2              :  1;
            __IO uint32_t PRBE3              :  1;
            __IO uint32_t PRUM0              :  1;
            __IO uint32_t PRUM1              :  1;
            __IO uint32_t PRUM2              :  1;
            __IO uint32_t PRUM3              :  1;
            __IO uint32_t PUR0               :  1;
            __IO uint32_t PUR1               :  1;
            __IO uint32_t PUR2               :  1;
            __IO uint32_t PUR3               :  1;
            __IO uint32_t                    :  4;
            __IO uint32_t CR1BE              :  1;
            __IO uint32_t CR1UEOP            :  1;
            __IO uint32_t CR1UTRG            :  1;
            __IO uint32_t                    : 13;
        } CR2_b;
    };
    union {
        __IO uint32_t TCR;                 /*!< Address Offset: 0x00C  EPWM Trigger Control Register  */
         struct {
            __IO uint32_t DEC0               :  4;
            __IO uint32_t UCE0               :  1;
            __IO uint32_t DCE0               :  1;
            __IO uint32_t                    :  2;
            __IO uint32_t DEC1               :  4;
            __IO uint32_t UCE1               :  1;
            __IO uint32_t DCE1               :  1;
            __IO uint32_t                    :  2;
            __IO uint32_t DEC2               :  4;
            __IO uint32_t UCE2               :  1;
            __IO uint32_t DCE2               :  1;
            __IO uint32_t                    :  2;
            __IO uint32_t DEC3               :  4;
            __IO uint32_t UCE3               :  1;
            __IO uint32_t DCE3               :  1;
            __IO uint32_t                    :  2;
        } TCR_b;
    };
    union {
        __IO uint32_t PER0;                 /*!< Address Offset: 0x010  EPWM Period Setting Register 0  */
         struct {
            __IO uint32_t PER                : 12;
            __IO uint32_t                    : 20;
        } PER0_b;
    };
    union {
        __IO uint32_t PER1;                 /*!< Address Offset: 0x014  EPWM Period Setting Register 1  */
         struct {
            __IO uint32_t PER                : 12;
            __IO uint32_t                    : 20;
        } PER1_b;
    };
    union {
        __IO uint32_t PER2;                 /*!< Address Offset: 0x018  EPWM Period Setting Register 2  */
         struct {
            __IO uint32_t PER                : 12;
            __IO uint32_t                    : 20;
        } PER2_b;
    };
    union {
        __IO uint32_t PER3;                 /*!< Address Offset: 0x01C  EPWM Period Setting Register 3  */
         struct {
            __IO uint32_t PER                : 12;
            __IO uint32_t                    : 20;
        } PER3_b;
    };
    union {
        __IO uint32_t CMP0;                 /*!< Address Offset: 0x020  EPWM Compare Setting Register 0  */
         struct {
            __IO uint32_t COMP               : 12;
            __IO uint32_t                    : 20;
        } CMP0_b;
    };
    union {
        __IO uint32_t CMP1;                 /*!< Address Offset: 0x024  EPWM Compare Setting Register 1  */
         struct {
            __IO uint32_t COMP               : 12;
            __IO uint32_t                    : 20;
        } CMP1_b;
    };
    union {
        __IO uint32_t CMP2;                 /*!< Address Offset: 0x028  EPWM Compare Setting Register 2  */
         struct {
            __IO uint32_t COMP               : 12;
            __IO uint32_t                    : 20;
        } CMP2_b;
    };
    union {
        __IO uint32_t CMP3;                 /*!< Address Offset: 0x02C  EPWM Compare Setting Register 3  */
         struct {
            __IO uint32_t COMP               : 12;
            __IO uint32_t                    : 20;
        } CMP3_b;
    };
    union {
        __IO uint32_t CAP0;                 /*!< Address Offset: 0x030  EPWM Capture Value Register 0  */
         struct {
            __IO uint32_t COMP               : 12;
            __IO uint32_t CDIR               :  1;
            __IO uint32_t                    :  3;
            __IO uint32_t CAPU               : 12;
            __IO uint32_t CDIRU              :  1;
            __IO uint32_t                    :  3;
        } CAP0_b;
    };
    union {
        __IO uint32_t CAP1;                 /*!< Address Offset: 0x034  EPWM Capture Value Register 1  */
         struct {
            __IO uint32_t COMP               : 12;
            __IO uint32_t CDIR               :  1;
            __IO uint32_t                    :  3;
            __IO uint32_t CAPU               : 12;
            __IO uint32_t CDIRU              :  1;
            __IO uint32_t                    :  3;
        } CAP1_b;
    };
    union {
        __IO uint32_t CAP2;                 /*!< Address Offset: 0x038  EPWM Capture Value Register 2  */
         struct {
            __IO uint32_t COMP               : 12;
            __IO uint32_t CDIR               :  1;
            __IO uint32_t                    :  3;
            __IO uint32_t CAPU               : 12;
            __IO uint32_t CDIRU              :  1;
            __IO uint32_t                    :  3;
        } CAP2_b;
    };
    union {
        __IO uint32_t CAP3;                 /*!< Address Offset: 0x03C  EPWM Capture Value Register 3  */
         struct {
            __IO uint32_t COMP               : 12;
            __IO uint32_t CDIR               :  1;
            __IO uint32_t                    :  3;
            __IO uint32_t CAPU               : 12;
            __IO uint32_t CDIRU              :  1;
            __IO uint32_t                    :  3;
        } CAP3_b;
    };
    union {
        __IO uint32_t TRG0;                 /*!< Address Offset: 0x040  EPWM Trigger Value Register  0  */
         struct {
            __IO uint32_t TRG                : 12;
            __IO uint32_t                    : 20;
        } TRG0_b;
    };
    union {
        __IO uint32_t TRG1;                 /*!< Address Offset: 0x044  EPWM Trigger Value Register  1  */
         struct {
            __IO uint32_t TRG                : 12;
            __IO uint32_t                    : 20;
        } TRG1_b;
    };
    union {
        __IO uint32_t TRG2;                 /*!< Address Offset: 0x048  EPWM Trigger Value Register  2  */
         struct {
            __IO uint32_t TRG                : 12;
            __IO uint32_t                    : 20;
        } TRG2_b;
    };
    union {
        __IO uint32_t TRG3;                 /*!< Address Offset: 0x04C  EPWM Trigger Value Register  3  */
         struct {
            __IO uint32_t TRG                : 12;
            __IO uint32_t                    : 20;
        } TRG3_b;
    };
    union {
        __IO uint32_t CNT0;                 /*!< Address Offset: 0x050  EPWM Counter Value Register 0  */
         struct {
            __IO uint32_t CNT                : 12;
            __IO uint32_t                    : 20;
        } CNT0_b;
    };
    union {
        __IO uint32_t CNT1;                 /*!< Address Offset: 0x054  EPWM Counter Value Register 1  */
         struct {
            __IO uint32_t CNT                : 12;
            __IO uint32_t                    : 20;
        } CNT1_b;
    };
    union {
        __IO uint32_t CNT2;                 /*!< Address Offset: 0x058  EPWM Counter Value Register 2  */
         struct {
            __IO uint32_t CNT                : 12;
            __IO uint32_t                    : 20;
        } CNT2_b;
    };
    union {
        __IO uint32_t CNT3;                 /*!< Address Offset: 0x05C  EPWM Counter Value Register 3  */
         struct {
            __IO uint32_t CNT                : 12;
            __IO uint32_t                    : 20;
        } CNT3_b;
    };
    union {
        __IO uint32_t MOT;                 /*!< Address Offset: 0x060  EPWM Minimum On-Time Register  */
         struct {
            __IO uint32_t MOT                : 12;
            __IO uint32_t                    :  4;
            __IO uint32_t MEN0               :  1;
            __IO uint32_t MEN1               :  1;
            __IO uint32_t MEN2               :  1;
            __IO uint32_t MEN3               :  1;
            __IO uint32_t                    : 12;
        } MOT_b;
    };
    union {
        __IO uint32_t OC;                 /*!< Address Offset: 0x064  EPWM Over Current Register  */
         struct {
            __IO uint32_t OC0                :  1;
            __IO uint32_t OC1                :  1;
            __IO uint32_t OC2                :  1;
            __IO uint32_t OC3                :  1;
            __IO uint32_t                    : 28;
        } OC_b;
    };
    union {
        __IO uint32_t CM;                 /*!< Address Offset: 0x068  EPWM Counter Max Latched Register  */
         struct {
            __IO uint32_t CM0                :  1;
            __IO uint32_t CM1                :  1;
            __IO uint32_t CM2                :  1;
            __IO uint32_t CM3                :  1;
            __IO uint32_t                    : 28;
        } CM_b;
    };
    union {
        __IO uint32_t CD;                 /*!< Address Offset: 0x06C  EPWM Counter Direction Register  */
         struct {
            __IO uint32_t CD0                :  1;
            __IO uint32_t CD1                :  1;
            __IO uint32_t CD2                :  1;
            __IO uint32_t CD3                :  1;
            __IO uint32_t                    : 28;
        } CD_b;
    };
    union {
        __IO uint32_t IEN0;                 /*!< Address Offset: 0x070  EPWM Interrupt Enable Register 0  */
         struct {
            __IO uint32_t EOP0               :  1;
            __IO uint32_t CMP0               :  1;
            __IO uint32_t CAP0               :  1;
            __IO uint32_t TRG0               :  1;
            __IO uint32_t OC0                :  1;
            __IO uint32_t                    : 27;
        } IEN0_b;
    };
    union {
        __IO uint32_t IEN1;                 /*!< Address Offset: 0x074  EPWM Interrupt Enable Register 1  */
         struct {
            __IO uint32_t EOP1               :  1;
            __IO uint32_t CMP1               :  1;
            __IO uint32_t CAP1               :  1;
            __IO uint32_t TRG1               :  1;
            __IO uint32_t OC1                :  1;
            __IO uint32_t                    : 27;
        } IEN1_b;
    };
    union {
        __IO uint32_t IEN2;                 /*!< Address Offset: 0x078  EPWM Interrupt Enable Register 2  */
         struct {
            __IO uint32_t EOP2               :  1;
            __IO uint32_t CMP2               :  1;
            __IO uint32_t CAP2               :  1;
            __IO uint32_t TRG2               :  1;
            __IO uint32_t OC2                :  1;
            __IO uint32_t                    : 27;
        } IEN2_b;
    };
    union {
        __IO uint32_t IEN3;                 /*!< Address Offset: 0x07C  EPWM Interrupt Enable Register 3  */
         struct {
            __IO uint32_t EOP3               :  1;
            __IO uint32_t CMP3               :  1;
            __IO uint32_t CAP3               :  1;
            __IO uint32_t TRG3               :  1;
            __IO uint32_t OC3                :  1;
            __IO uint32_t                    : 27;
        } IEN3_b;
    };
    union {
        __IO uint32_t IPND0;                 /*!< Address Offset: 0x080  EPWM Interrupt Pending Register 0  */
         struct {
            __IO uint32_t EOP0               :  1;
            __IO uint32_t CMP0               :  1;
            __IO uint32_t CAP0               :  1;
            __IO uint32_t TRG0               :  1;
            __IO uint32_t OC0                :  1;
            __IO uint32_t                    : 27;
        } IPND0_b;
    };
    union {
        __IO uint32_t IPND1;                 /*!< Address Offset: 0x084  EPWM Interrupt Pending Register 1  */
         struct {
            __IO uint32_t EOP0               :  1;
            __IO uint32_t CMP0               :  1;
            __IO uint32_t CAP0               :  1;
            __IO uint32_t TRG0               :  1;
            __IO uint32_t OC0                :  1;
            __IO uint32_t                    : 27;
        } IPND1_b;
    };
    union {
        __IO uint32_t IPND2;                 /*!< Address Offset: 0x088  EPWM Interrupt Pending Register 2  */
         struct {
            __IO uint32_t EOP2               :  1;
            __IO uint32_t CMP2               :  1;
            __IO uint32_t CAP2               :  1;
            __IO uint32_t TRG2               :  1;
            __IO uint32_t OC2                :  1;
            __IO uint32_t                    : 27;
        } IPND2_b;
    };
    union {
        __IO uint32_t IPND3;                 /*!< Address Offset: 0x08C  EPWM Interrupt Pending Register 3  */
         struct {
            __IO uint32_t EOP3               :  1;
            __IO uint32_t CMP3               :  1;
            __IO uint32_t CAP3               :  1;
            __IO uint32_t TRG3               :  1;
            __IO uint32_t OC3                :  1;
            __IO uint32_t                    : 27;
        } IPND3_b;
    };
    union {
        __IO uint32_t EIPND0;                 /*!< Address Offset: 0x090  EPWM Enabled Interrupt Pending Register 0  */
         struct {
            __IO uint32_t EOP0               :  1;
            __IO uint32_t CMP0               :  1;
            __IO uint32_t CAP0               :  1;
            __IO uint32_t TRG0               :  1;
            __IO uint32_t OC0                :  1;
            __IO uint32_t                    : 27;
        } EIPND0_b;
    };
    union {
        __IO uint32_t EIPND1;                 /*!< Address Offset: 0x094  EPWM Enabled Interrupt Pending Register 1  */
         struct {
            __IO uint32_t EOP1               :  1;
            __IO uint32_t CMP1               :  1;
            __IO uint32_t CAP1               :  1;
            __IO uint32_t TRG1               :  1;
            __IO uint32_t OC1                :  1;
            __IO uint32_t                    : 27;
        } EIPND1_b;
    };
    union {
        __IO uint32_t EIPND2;                 /*!< Address Offset: 0x098  EPWM Enabled Interrupt Pending Register 2  */
         struct {
            __IO uint32_t EOP2               :  1;
            __IO uint32_t CMP2               :  1;
            __IO uint32_t CAP2               :  1;
            __IO uint32_t TRG2               :  1;
            __IO uint32_t OC2                :  1;
            __IO uint32_t                    : 27;
        } EIPND2_b;
    };
    union {
        __IO uint32_t EIPND3;                 /*!< Address Offset: 0x09C  EPWM Enabled Interrupt Pending Register 3  */
         struct {
            __IO uint32_t EOP3               :  1;
            __IO uint32_t CMP3               :  1;
            __IO uint32_t CAP3               :  1;
            __IO uint32_t TRG3               :  1;
            __IO uint32_t OC3                :  1;
            __IO uint32_t                    : 27;
        } EIPND3_b;
    };
} EPWM_TypeDef;
/**
  * @brief SPI (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t CR;                 /*!< Address Offset: 0x000  SPI control register   */
         struct {
            __IO uint32_t EN                 :  1;
            __IO uint32_t CPHA               :  1;
            __IO uint32_t CPOL               :  1;
            __IO uint32_t LSBF               :  1;
            __IO uint32_t DWID               :  2;
            __IO uint32_t WMODE              :  1;
            __IO uint32_t SMODE              :  1;
            __IO uint32_t SPIC               :  4;
            __IO uint32_t TXFCV              :  4;
            __IO uint32_t RXFCV              :  4;
            __IO uint32_t TXFCLR             :  1;
            __IO uint32_t RXFCLR             :  1;
            __IO uint32_t                    : 10;
        } CR_b;
    };
    union {
        __IO uint32_t SR;                 /*!< Address Offset: 0x004  SPI Status Register  */
         struct {
            __IO uint32_t BUSY               :  1;
            __IO uint32_t                    :  3;
            __IO uint32_t TXFE               :  1;
            __IO uint32_t TXFF               :  1;
            __IO uint32_t TXFC               :  1;
            __IO uint32_t TXFO               :  1;
            __IO uint32_t TXFLVL             :  4;
            __IO uint32_t RXFE               :  1;
            __IO uint32_t RXFF               :  1;
            __IO uint32_t RXFC               :  1;
            __IO uint32_t RXFO               :  1;
            __IO uint32_t RXFLVL             :  4;
            __IO uint32_t                    : 12;
        } SR_b;
    };
    union {
        __IO uint32_t TXF;                 /*!< Address Offset: 0x008  SPI TX FIFO Data Register   */
         struct {
            __IO uint32_t DATA               : 32;
        } TXF_b;
    };
    union {
        __IO uint32_t RXF;                 /*!< Address Offset: 0x00C  SPI RX FIFO Data Register   */
         struct {
            __IO uint32_t DATA               : 32;
        } RXF_b;
    };
    union {
        __IO uint32_t IEN;                 /*!< Address Offset: 0x010  SPI Interrupt Enable Registerr  */
         struct {
            __IO uint32_t TXFE               :  1;
            __IO uint32_t TXFNF              :  1;
            __IO uint32_t TXFC               :  1;
            __IO uint32_t TXFO               :  1;
            __IO uint32_t RXFNE              :  1;
            __IO uint32_t RXFF               :  1;
            __IO uint32_t RXFC               :  1;
            __IO uint32_t RXFO               :  1;
            __IO uint32_t                    : 24;
        } IEN_b;
    };
    union {
        __IO uint32_t IPND;                 /*!< Address Offset: 0x014  SPI Interrupt Pending Register  */
         struct {
            __IO uint32_t TXFE               :  1;
            __IO uint32_t TXFNF              :  1;
            __IO uint32_t TXFC               :  1;
            __IO uint32_t TXFO               :  1;
            __IO uint32_t RXFNE              :  1;
            __IO uint32_t RXFF               :  1;
            __IO uint32_t RXFC               :  1;
            __IO uint32_t RXFO               :  1;
            __IO uint32_t                    : 24;
        } IPND_b;
    };
    union {
        __IO uint32_t EIPND;                 /*!< Address Offset: 0x018  SPI Enabled Interrupt Pending Register  */
         struct {
            __IO uint32_t TXFE               :  1;
            __IO uint32_t TXFNF              :  1;
            __IO uint32_t TXFC               :  1;
            __IO uint32_t TXFO               :  1;
            __IO uint32_t RXFNE              :  1;
            __IO uint32_t RXFF               :  1;
            __IO uint32_t RXFC               :  1;
            __IO uint32_t RXFO               :  1;
            __IO uint32_t                    : 24;
        } EIPND_b;
    };
} SPI_TypeDef;
/**
  * @brief LINUART (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t CR;                 /*!< Address Offset: 0x00   UART Control Register  */
         struct {
            __IO uint32_t TXRXE              :  1;
            __IO uint32_t                    :  1;
            __IO uint32_t TXFE               :  1;
            __IO uint32_t RXFE               :  1;
            __IO uint32_t UE                 :  1;
            __IO uint32_t                    :  2;
            __IO uint32_t STOP               :  1;
            __IO uint32_t                    :  6;
            __IO uint32_t PS                 :  1;
            __IO uint32_t PCE                :  1;
            __IO uint32_t AUTOBRR            :  1;
            __IO uint32_t LINMODE            :  1;
            __IO uint32_t TXFCOMP            :  4;
            __IO uint32_t RXFCOMP            :  4;
            __IO uint32_t TEST               :  2;
            __IO uint32_t BRRWINE            :  1;
            __IO uint32_t                    :  1;
            __IO uint32_t TXLOOPE            :  1;
            __IO uint32_t                    :  1;
        } CR_b;
    };
    union {
        __IO uint32_t BRR;                 /*!< Address Offset: 0x04  LINUART Baudrate Register  */
         struct {
            __IO uint32_t BRR                : 20;
            __IO uint32_t                    : 12;
        } BRR_b;
    };
    union {
        __IO uint32_t RDATA;                 /*!< Address Offset: 0x08  LINUART Read Data Register  */
         struct {
            __IO uint32_t RDATA              :  9;
            __IO uint32_t                    : 23;
        } RDATA_b;
    };
    union {
        __IO uint32_t TDATA;                 /*!< Address Offset: 0x0C  LINUART Transmit Data Register  */
         struct {
            __IO uint32_t TDATA              :  9;
            __IO uint32_t                    : 23;
        } TDATA_b;
    };
    union {
        __IO uint32_t IEN;                 /*!< Address Offset: 0x10  LIN Interrupt Status Enable Register  */
         struct {
            __IO uint32_t TXCIE              :  1;
            __IO uint32_t RXCIE              :  1;
            __IO uint32_t TXBUSYIE           :  1;
            __IO uint32_t RXOVIE             :  1;
            __IO uint32_t PEIE               :  1;
            __IO uint32_t BRROK              :  1;
            __IO uint32_t TXENDIE            :  1;
            __IO uint32_t FEIE               :  1;
            __IO uint32_t TIMEOUTIE          :  1;
            __IO uint32_t TXFOVIE            :  1;
            __IO uint32_t TXFFIE             :  1;
            __IO uint32_t RXFFIE             :  1;
            __IO uint32_t TXFEIE             :  1;
            __IO uint32_t RXFEIE             :  1;
            __IO uint32_t BRKIE              :  1;
            __IO uint32_t TXFLCIE            :  1;
            __IO uint32_t RXFLCIE            :  1;
            __IO uint32_t TXFCIE             :  1;
            __IO uint32_t TXERRIE            :  1;
            __IO uint32_t                    : 13;
        } IEN_b;
    };
    union {
        __IO uint32_t ISR;                 /*!< Address Offset: 0x14  LINART Interrupt Status Register  */
         struct {
            __IO uint32_t TXCIF              :  1;
            __IO uint32_t RXCIF              :  1;
            __IO uint32_t TXBIF              :  1;
            __IO uint32_t RXOVIF             :  1;
            __IO uint32_t PEIF               :  1;
            __IO uint32_t BRROKIF            :  1;
            __IO uint32_t TXENDIF            :  1;
            __IO uint32_t FEIF               :  1;
            __IO uint32_t TOIF               :  1;
            __IO uint32_t TXFOVIF            :  1;
            __IO uint32_t TXFFIF             :  1;
            __IO uint32_t RXFFIF             :  1;
            __IO uint32_t TXFEIF             :  1;
            __IO uint32_t RXFEIF             :  1;
            __IO uint32_t BRKIF              :  1;
            __IO uint32_t TXFLIF             :  1;
            __IO uint32_t RXFLIF             :  1;
            __IO uint32_t TXFCIF             :  1;
            __IO uint32_t TXERRIF            :  1;
            __IO uint32_t TXFFILEVELF        :  5;
            __IO uint32_t RXFFILEVELF        :  5;
            __IO uint32_t BRRERRF            :  1;
            __IO uint32_t                    :  2;
        } ISR_b;
    };
    union {
        __IO uint32_t RXFIFO;                 /*!< Address Offset: 0x18  LINUART RX FIFO Register  */
         struct {
            __IO uint32_t RXFIFO             :  9;
            __IO uint32_t                    : 23;
        } RXFIFO_b;
    };
    union {
        __IO uint32_t TXFIFO;                 /*!< Address Offset: 0x1C  LINUART TX FIFO Register  */
         struct {
            __IO uint32_t TXFIFO             :  9;
            __IO uint32_t                    : 23;
        } TXFIFO_b;
    };
    union {
        __IO uint32_t TIMEOUT;                 /*!< Address Offset: 0x20  LINUART Timeout Register  */
         struct {
            __IO uint32_t TIMEOUT            : 21;
            __IO uint32_t                    : 11;
        } TIMEOUT_b;
    };
} LINUART_TypeDef;
/**
  * @brief LINPORT (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t BSMCR;                 /*!< Address Offset: 0x00  LIN Bus shunt Method Control Register  */
         struct {
            __IO uint32_t AUTOEN             :  1;
            __IO uint32_t SWPU               :  1;
            __IO uint32_t SWCS0              :  1;
            __IO uint32_t SWCS1              :  1;
            __IO uint32_t SWCS2              :  1;
            __IO uint32_t                    : 27;
        } BSMCR_b;
    };
    union {
        __IO uint32_t IEN;                 /*!< Address Offset: 0x04  LIN Interrupt Status Enable Register  */
         struct {
            __IO uint32_t LINFEIE            :  1;
            __IO uint32_t LINREIE            :  1;
            __IO uint32_t OCIE               :  1;
            __IO uint32_t DOMTOIE            :  1;
            __IO uint32_t BENDIE             :  1;
            __IO uint32_t                    : 27;
        } IEN_b;
    };
    union {
        __IO uint32_t ISR;                 /*!< Address Offset: 0x08  LIN Interrupt Status Register  */
         struct {
            __IO uint32_t LINFEIF            :  1;
            __IO uint32_t LINREIF            :  1;
            __IO uint32_t OCIF               :  1;
            __IO uint32_t DOMTOIF            :  1;
            __IO uint32_t BENDIF             :  1;
            __IO uint32_t                    : 27;
        } ISR_b;
    };
    __IO uint32_t reserved0;
    union {
        __IO uint32_t DIO;                 /*!< Address Offset: 0x10  LIN Data Input/Output Register  */
         struct {
            __IO uint32_t LINDI              :  1;
            __IO uint32_t LINDO              :  1;
            __IO uint32_t                    : 30;
        } DIO_b;
    };
    union {
        __IO uint32_t CR;                 /*!< Address Offset: 0x14  LIN control register   */
         struct {
            __IO uint32_t RXFT               :  4;
            __IO uint32_t OCFT               :  2;
            __IO uint32_t LAIS               :  1;
            __IO uint32_t PAIS               :  1;
            __IO uint32_t TXOS               :  2;
            __IO uint32_t SR                 :  2;
            __IO uint32_t DOMTOEN            :  1;
            __IO uint32_t LOM                :  1;
            __IO uint32_t                    :  1;
            __IO uint32_t LINPORTEN          :  1;
            __IO uint32_t RXEN               :  1;
            __IO uint32_t                    : 15;
        } CR_b;
    };
    union {
        __IO uint32_t TIMEOUT;                 /*!< Address Offset: 0x18  LIN TX Timeout Register  */
         struct {
            __IO uint32_t TIMEOUT            : 22;
            __IO uint32_t                    : 10;
        } TIMEOUT_b;
    };
} LINPORT_TypeDef;
/**
  * @brief PWMIO (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t CR;                 /*!< Address Offset: 0x000  PWMIO Control Register  */
         struct {
            __IO uint32_t IENA               :  1;
            __IO uint32_t OENA               :  1;
            __IO uint32_t OM                 :  2;
            __IO uint32_t FDUPL              :  1;
            __IO uint32_t IDGL               :  1;
            __IO uint32_t ORBE               :  1;
            __IO uint32_t EDFEN              :  1;
            __IO uint32_t ICLK               :  4;
            __IO uint32_t OCLK               :  4;
            __IO uint32_t                    : 16;
        } CR_b;
    };
    __IO uint32_t reserved0;
    __IO uint32_t reserved1;
    __IO uint32_t reserved2;
    union {
        __IO uint32_t IHT;                 /*!< Address Offset: 0x010  PWMIO Input High Time Register  */
         struct {
            __IO uint32_t IHT                : 14;
            __IO uint32_t                    : 18;
        } IHT_b;
    };
    union {
        __IO uint32_t ILT;                 /*!< Address Offset: 0x014  PWMIO Input Low Time Register  */
         struct {
            __IO uint32_t ILT                : 14;
            __IO uint32_t                    : 18;
        } ILT_b;
    };
    union {
        __IO uint32_t ICNT;                 /*!< Address Offset: 0x018  PWMIO Input Counter Register  */
         struct {
            __IO uint32_t ICNT               : 14;
            __IO uint32_t                    : 18;
        } ICNT_b;
    };
    __IO uint32_t reserved3;
    union {
        __IO uint32_t OPT;                 /*!< Address Offset: 0x020  PWMIO Output Period / Pause Time Register  */
         struct {
            __IO uint32_t OPT                : 14;
            __IO uint32_t                    : 18;
        } OPT_b;
    };
    union {
        __IO uint32_t OLT;                 /*!< Address Offset: 0x024  PWMIO Output Low Time Register  */
         struct {
            __IO uint32_t OLT                : 14;
            __IO uint32_t                    : 18;
        } OLT_b;
    };
    union {
        __IO uint32_t OCNT;                 /*!< Address Offset: 0x028  PWMIO Output Counter Register  */
         struct {
            __IO uint32_t OCNT               : 14;
            __IO uint32_t                    : 18;
        } OCNT_b;
    };
    __IO uint32_t reserved4;
    union {
        __IO uint32_t IEN;                 /*!< Address Offset: 0x030  PWMIO Interrupt Enable Register  */
         struct {
            __IO uint32_t IRE                :  1;
            __IO uint32_t IFE                :  1;
            __IO uint32_t ICOF               :  1;
            __IO uint32_t OEOP               :  1;
            __IO uint32_t                    : 28;
        } IEN_b;
    };
    union {
        __IO uint32_t IPND;                 /*!< Address Offset: 0x034  PWMIO Interrupt Pending Register  */
         struct {
            __IO uint32_t IRE                :  1;
            __IO uint32_t IFE                :  1;
            __IO uint32_t ICOF               :  1;
            __IO uint32_t OEOP               :  1;
            __IO uint32_t                    : 28;
        } IPND_b;
    };
    union {
        __IO uint32_t EIPND;                 /*!< Address Offset: 0x038  PWMIO Enabled Interrupt Pending Register  */
         struct {
            __IO uint32_t IRE                :  1;
            __IO uint32_t IFE                :  1;
            __IO uint32_t ICOF               :  1;
            __IO uint32_t OEOP               :  1;
            __IO uint32_t                    : 28;
        } EIPND_b;
    };
} PWMIO_TypeDef;
/**
  * @brief TIMER (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t CR;                 /*!< Address Offset: 0x000  Timer Counter Control Register  */
         struct {
            __IO uint32_t CEN                :  1;
            __IO uint32_t UDIS               :  1;
            __IO uint32_t URS                :  1;
            __IO uint32_t MS                 :  1;
            __IO uint32_t ARPE               :  1;
            __IO uint32_t                    :  3;
            __IO uint32_t OVIE               :  1;
            __IO uint32_t UIE                :  1;
            __IO uint32_t                    :  2;
            __IO uint32_t CKSRC              :  2;
            __IO uint32_t                    : 18;
        } CR_b;
    };
    union {
        __IO uint32_t CCCR;                 /*!< Address Offset: 0x004  Timer Capture/Compare Control Register  */
         struct {
            __IO uint32_t CCE                :  1;
            __IO uint32_t CCP                :  2;
            __IO uint32_t CCS                :  1;
            __IO uint32_t OCPE               :  1;
            __IO uint32_t ICSRC              :  3;
            __IO uint32_t ICIE               :  1;
            __IO uint32_t ICOIE              :  1;
            __IO uint32_t OCIE               :  1;
            __IO uint32_t                    :  1;
            __IO uint32_t OCM                :  3;
            __IO uint32_t                    : 17;
        } CCCR_b;
    };
    union {
        __IO uint32_t ERG;                 /*!< Address Offset: 0x008  Timer Manuel Event Generation Register  */
         struct {
            __IO uint32_t UG                 :  1;
            __IO uint32_t                    :  7;
            __IO uint32_t CCG                :  1;
            __IO uint32_t                    : 23;
        } ERG_b;
    };
    union {
        __IO uint32_t ICFR;                 /*!< Address Offset: 0x00C  Timer Input Capture Filter Register  */
         struct {
            __IO uint32_t ICF                :  8;
            __IO uint32_t                    : 24;
        } ICFR_b;
    };
    union {
        __IO uint32_t IPND;                 /*!< Address Offset: 0x010  Timer Pending Register  */
         struct {
            __IO uint32_t UIF                :  1;
            __IO uint32_t OCIF               :  1;
            __IO uint32_t ICIF               :  1;
            __IO uint32_t ICOIF              :  1;
            __IO uint32_t OVIF               :  1;
            __IO uint32_t                    : 27;
        } IPND_b;
    };
    union {
        __IO uint32_t EIPND;                 /*!< Address Offset: 0x014  Timer Enable Pending Register  */
         struct {
            __IO uint32_t EUIF               :  1;
            __IO uint32_t EOCIF              :  1;
            __IO uint32_t EICIF              :  1;
            __IO uint32_t EICOIF             :  1;
            __IO uint32_t EOVIF              :  1;
            __IO uint32_t                    : 27;
        } EIPND_b;
    };
    __IO uint32_t reserved0;
    __IO uint32_t reserved1;
    union {
        __IO uint32_t CSVR;                 /*!< Address Offset: 0x020  Timer Counter Start Register  */
         struct {
            __IO uint32_t CSVR               : 32;
        } CSVR_b;
    };
    union {
        __IO uint32_t CEVR;                 /*!< Address Offset: 0x024  Timer Counter End Register  */
         struct {
            __IO uint32_t CEVR               : 32;
        } CEVR_b;
    };
    union {
        __IO uint32_t CCR;                 /*!< Address Offset: 0x028  Timer Capture/Compare Register  */
         struct {
            __IO uint32_t CCR                : 32;
        } CCR_b;
    };
    union {
        __IO uint32_t PSCR;                 /*!< Address Offset: 0x02C  Timer Clock Division Register  */
         struct {
            __IO uint32_t PSC                : 16;
            __IO uint32_t                    : 16;
        } PSCR_b;
    };
    union {
        __IO uint32_t CNTR;                 /*!< Address Offset: 0x030  Timer Inside Counter Register  */
         struct {
            __IO uint32_t CNT                : 32;
        } CNTR_b;
    };
} TIMER_TypeDef;
/**
  * @brief CAPCOM (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t CCR;                 /*!< Address Offset: 0x000  CAPCOM Control Register  */
         struct {
            __IO uint32_t EN                 :  1;
            __IO uint32_t ARE                :  1;
            __IO uint32_t ACM                :  1;
            __IO uint32_t                    :  5;
            __IO uint32_t IAM0               :  2;
            __IO uint32_t OAM0               :  2;
            __IO uint32_t CIF0               :  3;
            __IO uint32_t CIS0               :  1;
            __IO uint32_t IAM1               :  2;
            __IO uint32_t OAM1               :  2;
            __IO uint32_t CIF1               :  3;
            __IO uint32_t CIS1               :  1;
            __IO uint32_t IAM2               :  2;
            __IO uint32_t OAM2               :  2;
            __IO uint32_t CIF2               :  3;
            __IO uint32_t CIS2               :  1;
        } CCR_b;
    };
    union {
        __IO uint32_t CCNTR;                 /*!< Address Offset: 0x004  CAPCOM Counter Register  */
         struct {
            __IO uint32_t CCNT               : 16;
            __IO uint32_t                    : 16;
        } CCNTR_b;
    };
    union {
        __IO uint32_t CCDR;                 /*!< Address Offset: 0x008  CAPCOM Clock Division Register  */
         struct {
            __IO uint32_t TDV                : 16;
            __IO uint32_t                    : 16;
        } CCDR_b;
    };
    __IO uint32_t reserved0;
    union {
        __IO uint32_t CCMPR0;                 /*!< Address Offset: 0x010  CAPCOM Compare Register 0  */
         struct {
            __IO uint32_t CMPR               : 16;
            __IO uint32_t                    : 16;
        } CCMPR0_b;
    };
    union {
        __IO uint32_t CCMPR1;                 /*!< Address Offset: 0x014  CAPCOM Compare Register 1  */
         struct {
            __IO uint32_t CMPR               : 16;
            __IO uint32_t                    : 16;
        } CCMPR1_b;
    };
    union {
        __IO uint32_t CCMPR2;                 /*!< Address Offset: 0x018  CAPCOM Compare Register 2  */
         struct {
            __IO uint32_t CMPR               : 16;
            __IO uint32_t                    : 16;
        } CCMPR2_b;
    };
    __IO uint32_t reserved1;
    union {
        __IO uint32_t CCAPR0;                 /*!< Address Offset: 0x020  CAPCOM Capture Register 0  */
         struct {
            __IO uint32_t CAPR               : 16;
            __IO uint32_t                    : 16;
        } CCAPR0_b;
    };
    union {
        __IO uint32_t CCAPR1;                 /*!< Address Offset: 0x024  CAPCOM Capture Register 1  */
         struct {
            __IO uint32_t CAPR               : 16;
            __IO uint32_t                    : 16;
        } CCAPR1_b;
    };
    union {
        __IO uint32_t CCAPR2;                 /*!< Address Offset: 0x028  CAPCOM Capture Register 2  */
         struct {
            __IO uint32_t CAPR               : 16;
            __IO uint32_t                    : 16;
        } CCAPR2_b;
    };
    __IO uint32_t reserved2;
    union {
        __IO uint32_t IEN;                 /*!< Address Offset: 0x030  CAPCOM Interrupt Enable Register  */
         struct {
            __IO uint32_t OVF0               :  1;
            __IO uint32_t CMP0               :  1;
            __IO uint32_t CAP0               :  1;
            __IO uint32_t CVF0               :  1;
            __IO uint32_t OVF1               :  1;
            __IO uint32_t CMP1               :  1;
            __IO uint32_t CAP1               :  1;
            __IO uint32_t CVF1               :  1;
            __IO uint32_t OVF2               :  1;
            __IO uint32_t CMP2               :  1;
            __IO uint32_t CAP2               :  1;
            __IO uint32_t CVF2               :  1;
            __IO uint32_t RP                 :  1;
            __IO uint32_t WP                 :  1;
            __IO uint32_t                    : 18;
        } IEN_b;
    };
    union {
        __IO uint32_t IPND;                 /*!< Address Offset: 0x034  CAPCOM Interrupt Status Register  */
         struct {
            __IO uint32_t OVF0               :  1;
            __IO uint32_t CMP0               :  1;
            __IO uint32_t CAP0               :  1;
            __IO uint32_t CVF0               :  1;
            __IO uint32_t OVF1               :  1;
            __IO uint32_t CMP1               :  1;
            __IO uint32_t CAP1               :  1;
            __IO uint32_t CVF1               :  1;
            __IO uint32_t OVF2               :  1;
            __IO uint32_t CMP2               :  1;
            __IO uint32_t CAP2               :  1;
            __IO uint32_t CVF2               :  1;
            __IO uint32_t RP                 :  1;
            __IO uint32_t WP                 :  1;
            __IO uint32_t                    : 18;
        } IPND_b;
    };
    union {
        __IO uint32_t EIPND;                 /*!< Address Offset: 0x038  CAPCOM Enable Interrupt Pending Register  */
         struct {
            __IO uint32_t OVF0               :  1;
            __IO uint32_t CMP0               :  1;
            __IO uint32_t CAP0               :  1;
            __IO uint32_t CVF0               :  1;
            __IO uint32_t OVF1               :  1;
            __IO uint32_t CMP1               :  1;
            __IO uint32_t CAP1               :  1;
            __IO uint32_t CVF1               :  1;
            __IO uint32_t OVF2               :  1;
            __IO uint32_t CMP2               :  1;
            __IO uint32_t CAP2               :  1;
            __IO uint32_t CVF2               :  1;
            __IO uint32_t RP                 :  1;
            __IO uint32_t WP                 :  1;
            __IO uint32_t                    : 18;
        } EIPND_b;
    };
} CAPCOM_TypeDef;
/**
  * @brief DWDG (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t DWKR;                 /*!< Address Offset: 0x000  DWDG Key Register  */
         struct {
            __IO uint32_t KEY                : 16;
            __IO uint32_t                    : 16;
        } DWKR_b;
    };
    union {
        __IO uint32_t DWPR;                 /*!< Address Offset: 0x004  DWDG Prescaler Register  */
         struct {
            __IO uint32_t PREDIV             :  3;
            __IO uint32_t                    : 29;
        } DWPR_b;
    };
    union {
        __IO uint32_t DWRR;                 /*!< Address Offset: 0x008  DWDG Reload Register  */
         struct {
            __IO uint32_t RELOAD             : 16;
            __IO uint32_t                    : 16;
        } DWRR_b;
    };
    union {
        __IO uint32_t DCCR;                 /*!< Address Offset: 0x00C  DWDG Count Register   */
         struct {
            __IO uint32_t PS                 : 16;
            __IO uint32_t                    : 16;
        } DCCR_b;
    };
} DWDG_TypeDef;
/**
  * @brief WWDG (novosense) 
 */
typedef struct {
    union {
        __IO uint32_t WPCR;                 /*!< Address Offset: 0x000  WWDG Wakeup Clock Register  */
         struct {
            __IO uint32_t WDPD               :  3;
            __IO uint32_t                    :  1;
            __IO uint32_t WKPD               :  3;
            __IO uint32_t                    : 25;
        } WPCR_b;
    };
    union {
        __IO uint32_t WWVR;                 /*!< Address Offset: 0x004  WWDG Window Register  */
         struct {
            __IO uint32_t WWV                : 16;
            __IO uint32_t                    : 16;
        } WWVR_b;
    };
    union {
        __IO uint32_t WTVR;                 /*!< Address Offset: 0x008  WWDG Trigger Register  */
         struct {
            __IO uint32_t WTV                :  8;
            __IO uint32_t                    : 24;
        } WTVR_b;
    };
    union {
        __IO uint32_t WCVR;                 /*!< Address Offset: 0x00C  WWDG Counter Register  */
         struct {
            __IO uint32_t TRG                :  8;
            __IO uint32_t                    : 24;
        } WCVR_b;
    };
    union {
        __IO uint32_t WSTR;                 /*!< Address Offset: 0x010  WWDG Status Register  */
         struct {
            __IO uint32_t BUSY               :  1;
            __IO uint32_t                    : 31;
        } WSTR_b;
    };
} WWDG_TypeDef;
 /******************************************************************************/
/*                         Peripheral memory map                              */
/******************************************************************************/
/* Peripheral and SRAM base address */ 
#define ROM_BASE                 (0x00000000)
#define RAM_BASE                 (0x20000000)
#define FLASH_BASE               (0x08000000)
#define FLASH_CTRL_BASE          (0x08020000)
#define Core_BASE                (0xE0000000)
#define SYSCTRL_BASE             (0x40020000)
#define GPIO_BASE                (0x40021000)
#define EEPROM_BASE              (0x40022000)
#define EEPROM_CTRL_BASE         (0x40022300)
#define ADC_BASE                 (0x40024000)
#define BEMFC_BASE               (0x40025000)
#define EPWM_BASE                (0x40026000)
#define SPI_BASE                 (0x40000000)
#define LINUART_BASE             (0x40001000)
#define LINPORT_BASE             (0x40002000)
#define PWMIO_BASE               (0x40003000)
#define TMR0_BASE                (0x40004000)
#define TMR1_BASE                (0x40005000)
#define CAPCOM_BASE              (0x40006000)
#define DWDG_BASE                (0x40008000)
#define WWDG_BASE                (0x40009000)
#define FLASH_DEBUG_BASE         (0x08010800)
/******************************************************************************/
/*                         Peripheral declaration                             */
/******************************************************************************/
#define FLASH_CTRL            ((FLASH_CONTROLLER_TypeDef *)FLASH_CTRL_BASE)
#define SYSCTRL               ((SYSCTRL_TypeDef *)     SYSCTRL_BASE)
#define GPIO                  ((GPIO_TypeDef *)        GPIO_BASE)
#define EEPROM_CTRL           ((EEPROM_CTRL_TypeDef *) EEPROM_CTRL_BASE)
#define ADC                   ((ADC_TypeDef *)         ADC_BASE)
#define BEMFC                 ((BEMFC_TypeDef *)       BEMFC_BASE)
#define EPWM                  ((EPWM_TypeDef *)        EPWM_BASE)
#define SPI                   ((SPI_TypeDef *)         SPI_BASE)
#define LINUART               ((LINUART_TypeDef *)     LINUART_BASE)
#define LINPORT               ((LINPORT_TypeDef *)     LINPORT_BASE)
#define PWMIO                 ((PWMIO_TypeDef *)       PWMIO_BASE)
#define TMR0                  ((TIMER_TypeDef *)       TMR0_BASE)
#define TMR1                  ((TIMER_TypeDef *)       TMR1_BASE)
#define CAPCOM                ((CAPCOM_TypeDef *)      CAPCOM_BASE)
#define DWDG                  ((DWDG_TypeDef *)        DWDG_BASE)
#define WWDG                  ((WWDG_TypeDef *)        WWDG_BASE)

#endif

